A. Field of the Invention
The invention relates to digital computer architecture and, more particularly, to means for interconnecting for communication with each other such diverse devices as processors, memory (main memory) and I/O devices such as mass storage (e.g. disks and tapes), console terminals, printers, and other such devices in a digital computer system. The particular invention claimed herein relates to a cache invalidation mechanism for multiprocessor systems.
B. Prior Art
As the cost of digital computer systems and their components continues to decrease, more and more different types of data handling devices are being interconnected into these systems. The devices have widely varying characteristics with respect to speed (i.e., the rate at which they can accept or transmit data), required control information, data format, and other such characteristics, yet they must communicate with each other. For example, processors must often communicate with main memory (very high speed), mass storage devices such as disk memory (high speed), and output devices such as printers (very low speed). An important aspect of any interconnecting means is its ability to support arbitration among the competing demands of devices wishing to communicate with each other. Some form of arbitration must be performed to grant a request for access to the communications path, and thus it is essential that the arbitration process be efficient, since it may otherwise consume an undue portion of the computer system's resources. Further, it is generally desirable that the arbitration process provide some measure of flexibility in allocating the communications path among the requesting devices. In environments which allow a wide variety of devices to be attached to the communications path, particularly in environments which additionally allow the connection of multiple processors to the communications path, the competing demands on the arbitration mechanism often lead to undesirable constraints on system operation and flexibility.
Another important aspect of an interconnecting means is its support of interrupts. The manner in which these interrupts are posted often results in significant restrictions on the achievable flexibility of device attachment to the communications path.
In addition to providing communications among devices attached to a single central processor, it is frequently desirable to provide access between such devices and one or more additional processors, as well as between the several processors themselves. This requirement of communication among processors adds substantially increased complexity to the interconnection problem because of the need to insure coordinated operation. One aspect of interprocessor communications that requires particular attention is the problem caused by utilization of caches on one or more of the processors. Such caches can cause processing errors if appropriate steps are not taken to insure that access to the cache is allowed only when the cached data is "valid", that is, has not been altered in main memory since it was cached. If cache control is not performed efficiently, the performance of the system as a whole may be significantly degraded.